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AD9208 Datenblatt(PDF) 1 Page - Analog Devices |
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AD9208 Datenblatt(HTML) 1 Page - Analog Devices |
1 / 137 page 14-Bit, 3 GSPS, JESD204B, Dual Analog-to-Digital Converter Data Sheet AD9208 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES JESD204B (Subclass 1) coded serial digital outputs Support for lane rates up to 16 Gbps per lane 1.65 W total power per channel at 3 GSPS (default settings) Performance at −2 dBFS amplitude, 2.6 GHz input SFDR = 70 dBFS SNR = 57.2 dBFS Performance at −9 dBFS amplitude, 2.6 GHz input SFDR = 78 dBFS SNR = 59.5 dBFS Integrated input buffer Noise density = −152 dBFS/Hz 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation 2 integrated, wideband digital processors per channel 48-bit NCO 4 cascaded half-band filters Phase coherent NCO switching Up to 4 channels available Serial port control Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither APPLICATIONS Diversity multiband and multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A Electronic test and measurement systems Phased array radar and electronic warfare DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers FUNCTIONAL BLOCK DIAGRAM ADC CORE FAST DETECT SIGNAL MONITOR DIGITAL DOWN- CONVERTER DIGITAL DOWN- CONVERTER 14 14 BUFFER VIN+A VIN–A VIN+B CLK+ CLK– VREF PDWN/STBY SYSREF± AGND DRGND DGND AVDD1 (0.975V) DVDD (0.975V) DRVDD1 (0.975V) DRVDD2 (1.9V) SPIVDD (1.9V) AVDD2 (1.9V) AVDD3 (2.5V) AVDD1_SR (0.975V) SPI AND CONTROL REGISTERS SDIO SCLK CSB VIN–B BUFFER ADC CORE ÷2 ÷4 AD9208 SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± SERDOUT4± SERDOUT5± SERDOUT6± SERDOUT7± JESD204B LINK AND Tx OUTPUTS 8 JESD204B SUBCLASS 1 CONTROL CLOCK DISTRIBUTION SYNCINB± GPIO_A1 FD_A/GPIO_A0 FD_B/GPIO_B0 GPIO_B1 GPIO MUX Figure 1. |
Ähnliche Teilenummer - AD9208 |
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Ähnliche Beschreibung - AD9208 |
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