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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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AD9690 Datenblatt(PDF) 8 Page - Analog Devices |
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AD9690 Datenblatt(HTML) 8 Page - Analog Devices |
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8 / 79 page  Data Sheet AD9690 Rev. B | Page 7 of 78 AD9690-500 AD9690-1000 Parameter1 Temperature Min Typ Max Min Typ Max Unit WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC3 fIN = 10 MHz 25°C −95 −95 dBFS fIN = 170 MHz Full −95 −82 −94 −81 dBFS fIN = 340 MHz 25°C −93 −88 dBFS fIN = 450 MHz 25°C −93 −86 dBFS fIN = 765 MHz 25°C −88 −81 dBFS fIN = 985 MHz 25°C −89 −82 dBFS fIN = 1950 MHz 25°C −84 −75 dBFS TWO-TONE INTERMODULATION DISTORTION (IMD), AIN1 AND AIN2 = −7 dBFS fIN1 = 185 MHz, fIN2 = 188 MHz 25°C −88 −87 dBFS fIN1 = 338 MHz, fIN2 = 341 MHz 25°C −88 −88 dBFS FULL POWER BANDWIDTH4 25°C 2 2 GHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Noise density is measured at a low analog input frequency (30 MHz). 3 See Table 10 for the recommended settings for full-scale voltage and buffer current. 4 Measured with the circuit shown in Figure 64. DIGITAL SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate for each speed grade, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 3. Parameter Temperature Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance Full LVDS/LVPECL Differential Input Voltage Full 600 1200 1800 mV p-p Input Common-Mode Voltage Full 0.85 V Input Resistance (Differential) Full 35 kΩ Input Capacitance Full 2.5 pF SYSREF INPUTS (SYSREF+, SYSREF−) Logic Compliance Full LVDS/LVPECL Differential Input Voltage Full 400 1200 1800 mV p-p Input Common-Mode Voltage Full 0.6 0.85 2.0 V Input Resistance (Differential) Full 35 kΩ Input Capacitance (Differential) Full 2.5 pF LOGIC INPUTS (SDI, SCLK, CSB, PDWN/STBY) Logic Compliance Full CMOS Logic 1 Voltage Full 0.8 × SPIVDD V Logic 0 Voltage Full 0 0.2 × SPIVDD V Input Resistance Full 30 kΩ LOGIC OUTPUT (SDIO) Logic Compliance Full CMOS Logic 1 Voltage (IOH = 800 µA) Full 0.8 × SPIVDD V Logic 0 Voltage (IOL = 50 µA) Full 0.2 × SPIVDD V SYNCIN INPUT (SYNCINB+/SYNCINB−) Logic Compliance Full LVDS/LVPECL/CMOS Differential Input Voltage Full 400 1200 1800 mV p-p Input Common-Mode Voltage Full 0.6 0.85 2.0 V Input Resistance (Differential) Full 35 kΩ Input Capacitance Full 2.5 pF |
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Ähnliche Beschreibung - AD9690 |
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