AD9257

Data Sheet

Rev. A | Page 6 of 40

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 4.

Parameter1, 2

Temp

Min

Typ

Max

Unit

CLOCK3

Input Clock Rate

Full

10

520

MHz

Conversion Rate

Full

10

40/65

MSPS

Full

12.5/7.69

ns

Full

12.5/7.69

ns

OUTPUT PARAMETERS3

Full

1.5

2.3

3.1

ns

Full

300

ps

Full

300

ps

Full

1.5

2.3

3.1

ns

Full

ns

Full

ps

Full

ps

Data to Data Skew

Full

±50

±200

ps

Wake-Up Time (Standby)

25°C

35

μs

Wake-Up Time (Power-Down)5

25°C

375

μs

Pipeline Latency

Full

16

Clock

cycles

APERTURE

25°C

1

ns

Aperture Uncertainty (Jitter)

25°C

0.1

ps rms

Out-of-Range Recovery Time

25°C

1

Clock

cycles

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured on standard FR-4 material.

3

Can be adjusted via the SPI.

4

5

Wake-up time is defined as the time required to return to normal operation from power-down mode.

TIMING SPECIFICATIONS

Table 5.

Parameter

Description

Limit

Unit

SYNC TIMING REQUIREMENTS

SYNC to rising edge of CLK+ setup time

0.24

ns typ

SYNC to rising edge of CLK+ hold time

0.40

ns typ

SPI TIMING REQUIREMENTS

See Figure 61

Setup time between the data and the rising edge of SCLK

2

ns min

Hold time between the data and the rising edge of SCLK

2

ns min

Period of the SCLK

40

ns min

Setup time between CSB and SCLK

2

ns min

Hold time between CSB and SCLK

2

ns min

SCLK pulse width high

10

ns min

SCLK pulse width low

10

ns min

Time required for the SDIO pin to switch from an input to an output

relative to the SCLK falling edge (not shown in Figure 61)

10

ns min

Time required for the SDIO pin to switch from an output to an input

relative to the SCLK rising edge (not shown in Figure 61)

10

ns min