Datenblatt-Suchmaschine für elektronische Bauteile |
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AD9684 Datenblatt(PDF) 10 Page - Analog Devices |
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AD9684 Datenblatt(HTML) 10 Page - Analog Devices |
10 / 65 page Data Sheet AD9684 D13 D0 D13 D0 CLK+ DCO± (DATA CLOCK OUTPUT) 0° PHASE ADJUST DCO± (DATA CLOCK OUTPUT) 90° PHASE ADJUST1 DCO± (DATA CLOCK OUTPUT) 180° PHASE ADJUST DCO± (DATA CLOCK OUTPUT) 270° PHASE ADJUST2 SYNC+ APERTURE DELAY N N + x N – 1 N + y N + 35 N + 36 N + 37 N + 38 SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET D0± D13± FIXED DELAY FROM SYNC EVENT TO DCO KNOWN PHASE CONVERTER 0 SAMPLE [N] N + 39 N + 40 N + 41 VIN±x 190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±. 2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±. STATUS STATUS D13 D0 STATUS D13 D0 STATUS D13 D0 STATUS D13 D0 STATUS D13 D0 STATUS CLK– SYNC– STATUS+ (OVERRANGE/STATUS BIT) STATUS– tCLK tDCO tPD tSKEWR CONVERTER 0 SAMPLE [N + 1] CONVERTER 0 SAMPLE [N + 2] CONVERTER 0 SAMPLE [N + 3] CONVERTER 0 SAMPLE [N + 4] tSKEWF CONSTANT LATENCY = X CLK CYCLES Figure 4. Parallel Interleaved Mode—One Converter, ≤14-Bit Data Rev. 0 | Page 9 of 64 |
Ähnliche Teilenummer - AD9684 |
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Ähnliche Beschreibung - AD9684 |
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