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AD9251BCPZRL7-80 Datenblatt(PDF) 9 Page - Analog Devices

Teilenummer AD9251BCPZRL7-80
Bauteilbeschribung  1.8 V Dual Analog-to-Digital Converter
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9251BCPZRL7-80 Datenblatt(HTML) 9 Page - Analog Devices

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AD9251
Data Sheet
Rev. A | Page 8 of 36
TIMING SPECIFICATIONS
Table 5.
Parameter
Conditions
Min
Typ
Max
Unit
SYNC TIMING REQUIREMENTS
tSSYNC
SYNC to rising edge of CLK setup time
0.24
ns
tHSYNC
SYNC to rising edge of CLK hold time
0.40
ns
SPI TIMING REQUIREMENTS
tDS
Setup time between the data and the rising edge of SCLK
2
ns
tDH
Hold time between the data and the rising edge of SCLK
2
ns
tCLK
Period of the SCLK
40
ns
tS
Setup time between CSB and SCLK
2
ns
tH
Hold time between CSB and SCLK
2
ns
tHIGH
SCLK pulse width high
10
ns
tLOW
SCLK pulse width low
10
ns
tEN_SDIO
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
10
ns
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
10
ns
Timing Diagrams
tPD
tSKEW
tCH
tDCO
tCLK
N – 9
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
N – 8
N – 7
N – 6
N – 5
VIN
CLK+
CLK–
CH A/CH B DATA
DCOA/DCOB
tA
Figure 2. CMOS Output Data Timing
tPD
tSKEW
tCH
tDCO
tCLK
CH A
N – 9
CH B
N – 9
CH A
N – 8
CH B
N – 8
CH A
N – 7
CH B
N – 7
CH A
N – 6
CH B
N – 6
CH A
N – 5
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
VIN
CLK+
CLK–
CH A/CH B DATA
AS APPEARS ON
CH A OUTPUT PINS
DCOA/DCOB
tA
Figure 3. CMOS Interleaved Output Timing, Output as Appears on Channel A Output Pins


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