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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADS8598HIPMR Datenblatt(PDF) 10 Page - Texas Instruments |
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ADS8598HIPMR Datenblatt(HTML) 10 Page - Texas Instruments |
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10 / 64 page  10 ADS8598H SBAS829 – SEPTEMBER 2017 www.ti.com Product Folder Links: ADS8598H Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 6.6 Timing Requirements: CONVST Control minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), BUSY load = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 1) MIN NOM MAX UNIT tACQ Acquisition time: BUSY falling edge to rising edge of trailing CONVSTA or CONVSTB 0.7 µs tPH_CN CONVSTA, CONVSTB pulse high time 25 ns tPL_CN CONVSTA, CONVSTB pulse low time 25 ns tSU_BSYCS Setup time: BUSY falling to CS falling 0 ns tSU_RSTCN Setup time: RESET falling to first rising edge of CONVSTA or CONVSTB 25 ns tPH_RST RESET pulse high time 50 ns tD_CNAB Delay between rising edges of CONVSTA and CONVSTB 500 µs 6.7 Timing Requirements: Data Read Operation minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), BUSY load = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 2) MIN NOM MAX UNIT tDZ_CNCS Delay between CONVSTA, CONVSTB rising edge to CS falling edge, start of data read operation during conversion 10 ns tDZ_CSBSY Delay between CS rising edge to BUSY falling edge, end of data read operation during conversion 40 ns tSU_BSYCS Setup time: BUSY falling edge to CS falling edge, start of data read operation after conversion 0 ns tD_CSCN Delay between CS rising edge to CONVSTA, CONVSTB rising edge, end of data read operation after conversion 10 ns 6.8 Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 500 kSPS (unless otherwise noted) (see Figure 3) MIN NOM MAX UNIT tPH_CS, tPH_RD CS and RD high time 15 ns tPL_CS, tPL_RD CS and RD low time 15 ns tHT_RDDB, tHT_CSDB Hold time: RD and CS rising edge to DB[15:0] invalid 2.5 ns |
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Ähnliche Beschreibung - ADS8598HIPMR |
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