ADAU1781 datasheet(3/93 Pages) AD

Teilenummer	ADAU1781

Bauteilbeschribung	Low Noise Stereo Codec

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ADAU1781

Rev. B | Page 2 of 92

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Record Side Performance Specifications................................... 4

Output Side Performance Specifications................................... 6

Power Supply Specifications........................................................ 8

Typical Power Management Measurements ............................. 9

Digital Filters................................................................................. 9

Digital Input/Output Specifications......................................... 10

Digital Timing Specifications ................................................... 11

Absolute Maximum Ratings.......................................................... 14

Thermal Resistance .................................................................... 14

ESD Caution................................................................................ 14

Pin Configuration and Function Descriptions........................... 15

Typical Performance Characteristics ........................................... 17

System Block Diagrams ................................................................. 20

Theory of Operation ...................................................................... 24

Startup, Initialization, and Power................................................. 25

Power-Up Sequence ................................................................... 25

Clock Generation and Management........................................ 26

Enabling Digital Power to Functional Subsystems ................ 26

Setting Up the SigmaDSP Core ................................................ 26

Power Reduction Modes............................................................ 26

Power-Down Sequence.............................................................. 26

Clocking and Sampling Rates ....................................................... 27

Core Clock................................................................................... 27

Sampling Rates............................................................................ 27

PLL................................................................................................ 28

Record Signal Path.......................................................................... 30

Input Signal Path ........................................................................ 30

Analog-to-Digital Converters................................................... 31

Playback Signal Path ...................................................................... 32

Output Signal Paths ................................................................... 32

Digital-to-Analog Converters................................................... 32

Line Outputs ............................................................................... 32

Speaker Output........................................................................... 32

Control Ports................................................................................... 33

I2C Port ........................................................................................ 33

SPI Port........................................................................................ 36

Memory and Register Access.................................................... 36

Serial Data Input/Output Ports .................................................... 38

TDM Modes................................................................................ 38

General-Purpose Input/Outputs .................................................. 40

DSP Core ......................................................................................... 41

Signal Processing........................................................................ 41

Architecture ................................................................................ 41

Program Counter ....................................................................... 41

Features........................................................................................ 41

Numeric Formats ....................................................................... 42

Programming.............................................................................. 42

Program RAM, Parameter RAM, and Data RAM ..................... 44

Program RAM ............................................................................ 44

Parameter RAM.......................................................................... 44

Data RAM ................................................................................... 44

Read/Write Data Formats ......................................................... 44

Software Safeload ....................................................................... 45

Software Slew .............................................................................. 46

Applications Information .............................................................. 47

Power Supply Bypass Capacitors.............................................. 47

GSM Noise Filter........................................................................ 47

Grounding................................................................................... 47

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