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ADAU1781BCPZ-RL7 Datenblatt(PDF) 1 Page - Analog Devices |
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ADAU1781BCPZ-RL7 Datenblatt(HTML) 1 Page - Analog Devices |
1 / 93 page Low Noise Stereo Codec with SigmaDSP Processing Core ADAU1781 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved. FEATURES 24-bit stereo audio ADC and DAC 400 mW speaker amplifier (into 8 Ω load) Programmable SigmaDSP audio processing core Wind noise detection and filtering Enhanced stereo capture (ESC) Dynamics processing Equalization and filtering Volume control and mute Sampling rates from 8 kHz to 96 kHz Stereo pseudo differential microphone input Optional stereo digital microphone input pulse-density modulation (PDM) Stereo line output PLL supporting a range of input clock rates Analog and digital I/O 1.8 V to 3.3 V Software control via SigmaStudio graphical user interface Software-controllable, clickless mute Software register and hardware pin standby mode 32-lead, 5 mm × 5 mm LFCSP APPLICATIONS Digital still cameras Digital video cameras GENERAL DESCRIPTION The ADAU1781 is a low power, 24-bit stereo audio codec. The low noise DAC and ADC support sample rates from 8 kHz to 96 kHz. Low current draw and power saving modes make the ADAU1781 ideal for battery-powered audio applications. A programmable SigmaDSP® core provides enhanced record and playback processing to improve overall audio quality. The record path includes two digital stereo microphone inputs and an analog stereo input path. The analog inputs can be configured for either a pseudo differential or a single-ended stereo source. A dedicated analog beep input signal can be mixed into any output path. The ADAU1781 includes a stereo line output and speaker driver, which makes the device capable of supporting dynamic speakers. The serial control bus supports the I2C® or SPI protocols, and the serial audio bus is programmable for I2S, left-justified, right- justified, or TDM mode. A programmable PLL supports flexible clock generation for all standard rates and available master clocks from 11 MHz to 20 MHz. FUNCTIONAL BLOCK DIAGRAM PGA PGA LEFT ADC RIGHT ADC LEFT DAC RIGHT DAC PGA BEEP PDN MICBIAS LMIC/LMICN/ MICD1 LMICP RMIC/RMICN/ MICD2 RMICP AOUTL AOUTR SPP SPN PLL SigmaDSP CORE WIND NOISE NOTCH FILTER EQUALIZER DIGITAL VOLUME CONTROL DYNAMIC PROCESSING OUTPUT MIXER REGULATOR SERIAL DATA INPUT/OUTPUT PORTS I2C/SPI CONTROL PORT ADAU1781 MICROPHONE BIAS Figure 1. |
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