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AD7142 Datenblatt(PDF) 33 Page - Analog Devices |
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AD7142 Datenblatt(HTML) 33 Page - Analog Devices |
33 / 70 page Data Sheet AD7142 Rev. B | Page 33 of 70 SDI CW 15 CW 14 CW 13 CW 8 CW 1 CW 0 D15 D14 SCLK CW 12 NOTES 1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY. 2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS. 3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN). 4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED. 5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 0 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS) D1 D0 D1 D0 D15 DATA FOR STARTING REGISTER ADDRESS DATA FOR NEXT REGISTER ADDRESS D15 D14 1 32 23 4 15 16 17 18 31 34 33 48 47 49 CS CW 11 CW 10 CW 9 CW 7 CW 2 CW 6 CW 5 CW 4 CW 3 11 12 13 14 56 78 910 16-BIT COMMAND WORD ENABLE WORD R/W STARTING REGISTER ADDRESS Figure 47. Sequential Register Write SPI Timing NOTES 1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS. 2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS. 3. THE REGISTER DATA IS READ BACK ON THE SDO PIN. 4. X DENOTES DON’T CARE. 5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT. 6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK. 7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 1 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS) CW 11 CW 10 CW 13 CW 12 SDI CW 15 CW 14 CW 9 CW 7 CW 6 CW 5 CW 4 CW 3 CW 2 CW 1 CW 0 XX X CW 8 t1 t4 16-BIT READBACK DATA 5 32 6 7 8 9 10 11 12 13 14 15 16 30 31 t8 t5 SCLK 1234 XX X 17 18 19 CS XXX XXX XXX XXX SDO XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D2 D1 D0 XXX D15 D14 D13 t6 t7 XXX 16-BIT COMMAND WORD ENABLE WORD R/W REGISTER ADDRESS t2 t3 Figure 48. Single Register Readback SPI Timing Reading Data A read transaction begins when the master writes the command word to the AD7142 with the read/write bit set to 1. The master then supplies 16 clock pulses per data-word to be read, and the AD7142 clocks out data from the addressed register on the SDO line. The first data-word is clocked out on the first falling edge of SCLK following the command word, as shown in Figure 48. The AD7142 continues to clock out data on the SDO line provided the master continues to supply the clock signal on SCLK. The read transaction finishes when the master takes CS high. If the AD7142 address pointer reaches its maximum value, then the AD7142 repeatedly clocks out data from the addressed register. The address pointer does not wrap around. |
Ähnliche Teilenummer - AD7142_17 |
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Ähnliche Beschreibung - AD7142_17 |
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