AD73322L_17 datasheet(36/49 Pages) AD

Teilenummer	AD73322L

Bauteilbeschribung	Low Cost, Low Power CMOS General-Purpose Dual Analog Front

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AD73322L

Rev. A | Page 35 of 48

DIFFERENTIAL-TO-SINGLE-ENDED OUTPUT

In some applications it may be desirable to convert the full

differential output of the decoder channel to a single-ended

signal. The circuit of Figure 42 shows a scheme for doing this.

CONTINUOUS

TIME

LOW-PASS

FILTER

VREF

VINP1

VFBP1

VOUTP1

VOUTN1

AD73322L

+6/–15dB

PGA

0/38dB

PGA

GAIN

±1

REFOUT

REFCAP

REFERENCE

VREF

0.1

µF

RF

R1

RF

RLOAD

Figure 42. Example Circuit for Differential to Single-Ended

Output Conversion

DIGITAL INTERFACING

The AD73322L is designed to interface easily to most common

DSPs. The SCLK, SDO, SDOFS, SDI, and SDIFS must be con-

nected to the DSP’s serial clock, receive data, receive data

frame sync, transmit data, and transmit data frame sync pins,

respectively. The SE pin may be controlled from a parallel

output pin or flag pin such as FL0-2 on the ADSP-21xx (or XF

on the TMS320C5x) or, where SPORT power-down is not

required, it can be permanently strapped high using a suitable

pull-up resistor. The RESET pin may be connected to the

system hardware reset structure or it may also be controlled

using a dedicated control line. In the event of tying it to the

global system reset, it is advisable to operate the device in mixed

mode, which allows a software reset, otherwise there is no

convenient way of resetting the device. Figure 43 and Figure 44

show typical connections to an ADSP-218x and TMS320C5x,

respectively.

TFS

DT

SCLK

DR

RFS

ADSP-218x

DSP

AD73322L

CODEC

SDIFS

SDI

SCLK

SDO

SDOFS

FL0

FL1

RESET

SE

Figure 43. AD73322L Connected to ADSP-218x

FSX

DT

CLKX

DR

FSR

TMS320C5x

DSP

AD73322L

CODEC

SDIFS

SDI

SCLK

SDO

SDOFS

XF

RESET

SE

CLKR

Figure 44. AD73322L Connected to TMS320C5x

CASCADE OPERATION

Where it is required to configure a cascade of up to eight codecs

(four AD73322L dual codecs), ensure that the timing of the SE

and RESET signals is synchronized at each device in the

cascade. A simple D-type flip-flop is sufficient to sync each

signal to the master clock MCLK, as in Figure 45.

1/2

74HC74

CLK

DQ

DSP CONTROL

TO SE

MCLK

SE SIGNAL SYNCHRONIZED

TO MCLK

1/2

74HC74

CLK

DQ

DSP CONTROL

TO RESET

MCLK

RESET SIGNAL SYNCHRONIZED

TO MCLK

Figure 45. SE and RESET Sync Circuit or Cascaded Operation

Connection of a cascade of devices to a DSP, as shown in

Figure 46, is no more complicated than connecting a single

device. Instead of connecting the SDO and SDOFS to the DSP’s

Rx port, these are now daisy-chained to the SDI and SDIFS of

the next device in the cascade. The SDO and SDOFS of the final

device in the cascade are connected to the DSP’s Rx port to

complete the cascade. SE and RESET on all devices are fed from

the signals that were synchronized with the MCLK using the

circuit, as described previously. The SCLK from only one device

need be connected to the DSP’s SCLK input(s) as all devices run

at the same SCLK frequency and phase.

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