AD2S1210

Rev. A | Page 10 of 36

Pin

No.

Mnemonic

Description

13

DB13/SCLK

Data Bit 13/Serial Clock. In parallel mode, this pin acts as DB13, a three-state data output pin controlled by CS and RD. In

serial mode, this pin acts as the serial clock input.

14 to

17

DB12 to

DB9

Data Bit 12 to Data Bit 9. Three-state data output pins controlled by CS and RD.

18

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.

Decouple this pin to DGND. The voltage range on this pin is 2.3 V to 5.25 V and may be different to the voltage range

20

DB8

Data Bit 8. Three-state data output pin controlled by CS and RD.

21 to

28

DB7 to DB0

Data Bit 7 to Data Bit 0. Three-state data input/output pins controlled by CS, RD, and WR/FSYNC.

29

A

Incremental Encoder Emulation Output A. Logic output. This output is free running and is valid if the resolver format

input signals applied to the converter are valid.

30

B

Incremental Encoder Emulation Output B. Logic output. This output is free running and is valid if the resolver format

input signals applied to the converter are valid.

31

NM

North Marker Incremental Encoder Emulation Output. Logic output. This output is free running and is valid if the

resolver format input signals applied to the converter are valid.

32

DIR

Direction. Logic output. This output is used in conjunction with the incremental encoder emulation outputs. The DIR

output indicates the direction of the input rotation and is high for increasing angular rotation.

33

RESET

specified operating range of 4.75 V to 5.25 V.

34

LOT

Loss of Tracking. Logic output. LOT is indicated by a logic low on the LOT pin and is not latched. Refer to the Loss of

Position Tracking Detection section.

35

DOS

Degradation of Signal. Logic output. Degradation of signal (DOS) is detected when either resolver input (sine or cosine)

exceeds the specified DOS sine/cosine threshold or when an amplitude mismatch occurs between the sine and

cosine input voltages. DOS is indicated by a logic low on the DOS pin. Refer to the Signal Degradation Detection

section.

36

A1

Mode Select 1. Logic input. A1 in conjunction with A0 allows the mode of the AD2S1210 to be selected. Refer to the

Configuration of AD2S1210 section.

37

A0

Mode Select 0. Logic input. A0 in conjunction with A1 allows the mode of the AD2S1210 to be selected. Refer to the

Configuration of AD2S1210 section.

38

EXC

Excitation Frequency. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its

complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the excitation

frequency register.

39

EXC

Excitation Frequency Complement. Analog output. An on-board oscillator provides the sinusoidal excitation signal

(EXC) and its complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the

excitation frequency register.

40

AGND

Analog Ground. This pin is the ground reference points for analog circuitry on the AD2S1210. Refer all analog input

signals and any external reference signal to this AGND voltage. Connect the AGND pin to the AGND plane of a

system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V

apart, even on a transient basis.

41

SIN

Positive Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.

42

SINLO

Negative Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.

43

Analog Supply Voltage, 4.75 V to 5.25 V. This pin is the supply voltage for all analog circuitry on the AD2S1210. The

transient basis.

44

COSLO

Negative Analog Input of Differential COS/COSLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.

45

COS

Positive Analog Input of Differential COS/COSLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.

46

REFBYP

Reference Bypass. Connect reference decoupling capacitors at this pin. Typical recommended values are 10 μF and 0.01 μF.

47

REFOUT

Voltage Reference Output.

48

RES0

Resolution Select 0. Logic input. RES0 in conjunction with RES1 allows the resolution of the AD2S1210 to be

programmed. Refer to the Configuration of AD2S1210 section.