PRODUCT SPECIFICATION

FAN53180

REV. 1.0.0 6/10/03

3

Pin Configuration

Pin Definitions

Pin

Number Pin Name

Pin Function Description

1–6

VID[4:0],

VID5

VID Inputs. Determines the output voltage via the internal DAC. These inputs are

compliant to VRM10/VRD10 specifications for static and dynamic operation. All have

internal pull-ups so leaving them open results in logic high. Leaving VID[4:0] open results

in a “No CPU” condition disabling the PWM outputs.

7

FBRTN

Feedback Return. Error Amp and DAC reference point.

8FB

Feedback Input. Inverting input for Error Amp this pin is used for external compensation.

Can also be used to introduce DC offset voltage to the output.

9

COMP

Error Amp Output. This pin is used for external compensation.

10

PWRGD

Power Good Output. This is an open-drain output that asserts when the output voltage is

within the specified tolerance. It is expected to be pulled up to an external voltage rail.

11

EN

Output Enable. This is a dual-function pin. It allows for an external open-drain drain logic

signal to enable the output PWM.

12

DELAY

Soft-start and Current Limit Delay. An external resistor and capacitor sets the soft-start

ramp rate and the over-current latch off delay.

13

RT

Switching Frequency Adjust. This pin adjusts the output PWM switching frequency via

an external resistor.

14

RAMPADJ PWM Current Ramp Adjust. An external resistor to Vcc will adjust the amplitude of the

internal PWM ramp.

15

ILIMIT

Current Limit Adjust. An external resistor sets the current limit threshold for the regulator

circuit. This pin is internally pulled low when EN is low or the UVLO circuit is active.

16

CSREF

Current Sense Return. Inverting input of the current sense amp. Sense point for the

output voltage used for OVP, and PWRGD.

17

CSSUM

Current Sense Summing node. Non-inverting input of the current sense amp.

18

CSCOMP

Current Sense Compensation node. Output of the current sense amplifier. This pin is

used for droop compensation, a current loop reponse.

19

GND

Analog Chip Ground. Signal ground for the chip

20–23

SW[4:1]

Phase Current Sense/Balance inputs. Phase-to-phase current sense and balancing

inputs. Unused phases should be left open.

24–27

PWM[4:1]

PWM Outputs. CMOS outputs for driving external gate drivers such as the FAN53418.

Unused phases should be grounded.

28

VCC

Chip Power. Bias supply for the chip. Connect directly to a +12V supply. Bypass with a

1

µF MLCC capacitor.

DELAY

VID4

VID3

VID2

VID1

VID0

VID5

COMP

CSCOMP

PWRGD

EN

CSSUM

RT

VCC

SW2

SW3

PWM3

PWM4

PWM1

GND

FBRTN

ILIMIT

FB

CSREF

RAMPADJ

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

FAN53180

TSSOP-28

SW1

PWM2

SW4