Datenblatt-Suchmaschine für elektronische Bauteile |
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PYTHON480 Datenblatt(PDF) 40 Page - ON Semiconductor |
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PYTHON480 Datenblatt(HTML) 40 Page - ON Semiconductor |
40 / 69 page PYTHON 480 www.onsemi.com 40 Figure 32 shows shows the details of the readout of a number of lines for single window readout, at the beginning of the frame. Figure 32. LVDS Mode: Time Line for Single Window Readout (at the start of a frame) data channels sync channel data channels sync channel Sequencer Internal State line Ys line Ys+1 line Ye black timeslot Xstart Training TR FS ID IMG LE Training TR FOT ROT ROT ROT ID ROT CRC IMG IMG IMG IMG IMG timeslot Xstart + 1 timeslot Xend - 2 timeslot Xend - 1 timeslot Xend CRC timeslot Figure 33 shows the detail of the readout of a number of lines for readout of two overlapping windows. Figure 33. LVDS Mode: Time Line Showing the Readout of Two Overlapping Windows data channels sync channel data channels sync channel Sequencer Internal State line Ys+1 line Ye black timeslot XstartM Training TR LS IDM IMG LE Training TR FOT ROT ROT ROT IDN ROT CRC IMG LS IDN IMG IMG timeslot XstartN timeslot XendN line Ys IMG Frame Synchronization Table 29 shows the structure of the frame synchronization code. Note that the table shows the default data word (configurable). If more than one window is active at the same time, the sync channel transmits the frame synchronization codes of the window with highest index only. Table 29. FRAME SYNCHRONIZATION CODE DETAILS Sync Word Bit Position Register Address Default Value Description 9:7 N/A 0x4 Frame Sequence Start (FSS). Only sent out when reg_seq_fss_enable is asserted. 9:7 N/A 0x7 Frame Sequence End (FSE). Only sent out when reg_seq_fse_enable is asserted. 9:7 N/A 0x5 Frame start indication 9:7 N/A 0x6 Frame end indication 9:7 N/A 0x1 Line start indication 9:7 N/A 0x2 Line end indication 6:0 117[6:0] 0x2A These bits indicate that the received sync word is a frame synchronization code. The value is programmable by a register setting |
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