No. 7543-5/19

LB11690, 11690H

Three-Phase Logic Truth Table

Pin Assignments

• In the state where the high side gate is VH and the low side gate is VL, the high side FET

connected to the VH pin will be on and the low side FET connected to the UL pin will also be

on.

• Since the HP output is an open collector output, the high output level is the open state.

IN1

IN2

IN3

High side gate

Low side gate

HP

1

H

L

H

VH

UL

H

2

H

L

L

WH

UL

L

3

H

H

L

WH

VL

H

4

L

H

L

UH

VL

L

5

L

H

H

UH

WL

H

6

L

L

H

VH

WL

L

VB

VCC

LVS

CP1

CP2

RFGND

RF

WL

WOUT

HP

RC

FV

VOUT

VH

UL

UOUT

WH

VL

V12

V5

9

8

7

6

5

4

3

2

1

10

11

12

13

14

15

27

26

28

24

23

25

21

29

22

30

19

18

20

16

17

UH

IN1

IN2

IN3

GND

PWM

TOC

EI–

EI+

RES

LB11690

Top view

9

8

7

6

5

4

3

2

1

18

13

14

12

11

10

16

17

15

LB11690H

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

VB

GND

RF

GND

RF

WL

NC WOUT WH

VL

VOUT VH

UL UOUT UH

NC

IN1

IN2

IN3

NC

RES

EI+

EI–

TOC

PWM

FV

RC

HP

CP2

CP1

LVS

NC

V5

V12

NC

VCC

NC

FRAME

FRAME

Top view